Integrated circuits are continually becoming more complex. Because of increased complexity, integrated circuit substrates are required to have several doped regions of varying size and doping concentration. The doped regions may function as transistor current electrodes (i.e. source, drain, emitter, collector), transistor control electrodes (i.e. base and/or gate), interconnects, well regions, isolation regions, contact areas, and the like. If various integrated circuit technologies, such as complementary metal oxide semiconductor (CMOS) technologies, bipolar technologies, analog circuitry, high-power devices, memory elements (such as erasable programmable read only memory {EPROM}), are combined onto a single integrated circuit, an increased number of doped regions are usually required.
The formation of each doped region is performed sequentially. For example, an integrated circuit having a memory array of EPROMs, and supporting both bipolar and CMOS devices may require up to four well regions (one for the memory, two for the CMOS devices, and one for the bipolar devices) and may require numerous buried layers. Each well region may have a different optimal junction depth, optimal doping profile, and geometric shape. For these reasons, in order to optimize all of the four well regions, the four well regions are often formed independently and individually in a sequential fashion. Due to the independent formation, the alignment of well regions to each other is not always consistent. In addition, several photolithographic masking steps and diffusion steps (or implant steps) are required. The sequential process is therefore not time optimal or resource optimal.